FPGA PCIe, FMC and VPX Boards
Use standard PCIe, FMC/FMC+ and selected 3U VPX platforms for FPGA processing, high-speed data movement and modular application I/O.
| Platform category | Host or backplane | I/O architecture | Processing resources | Deployment |
|---|---|---|---|---|
| PCIe accelerator card | PCIe x4, x8 or x16, platform dependent | On-board I/O or FMC/FMC+ | FPGA DSP, protocol offload and DMA | Workstation or server |
| FMC/FMC+ module or carrier | PCIe or VPX carrier | ADC, DAC, RF, video or serial I/O | Converter interface and real-time processing | Laboratory and embedded systems |
| 3U VPX module | VPX payload or switch profile | FMC+, direct RF or backplane I/O | FPGA, SoC-FPGA or RFSoC | Rugged aerospace and defence |
Platform Capabilities
Limited custom-board scope
Power, memory, clocking and standard host interfaces are already implemented, leaving the project to focus on application logic and external I/O.
Modular converter and RF I/O
FMC and FMC+ mezzanines allow ADC, DAC, RF, video or networking functions to be selected separately from the FPGA carrier where supported.
Established host data paths
PCIe interfaces, DMA resources and reference designs provide a defined basis for moving data between FPGA, host, GPU and storage resources.
Multiple deployment formats
PCIe, FMC/FMC+ and selected 3U VPX options support laboratory, server and rugged embedded architectures with different cooling and backplane requirements.
Technical Features
PCIe accelerator boards
Install FPGA processing directly in a workstation or server with x4, x8 or x16 host links depending on the platform.
FMC and FMC+ modular I/O
Pair the processing board with application-specific ADC, DAC, RF, video or communication mezzanines.
Streaming DMA architecture
Move continuous buffers between FPGA memory, host memory, GPUs and storage with supported drivers and APIs.
Clock and synchronization resources
Use reference clocks, sample clocks and trigger paths for deterministic multi-channel acquisition and generation.
3U VPX deployment
Select payload, switch and SOSA-aligned options where rugged mechanics, backplane profiles and conduction cooling are required.
Reference designs and software
Use FPGA examples, host drivers and DMA APIs as the starting point for custom signal-processing pipelines.
Specifications
| Parameter | Unit | Value / Description |
|---|---|---|
| PROCESSING & FORM FACTOR | ||
| FPGA platforms | — | AMD and Altera FPGA, SoC-FPGA, adaptive SoC and RFSoC families, depending on board. |
| Board formats | — | PCIe add-in cards, FMC/FMC+ mezzanines or carriers, and 3U VPX plug-in modules. |
| Host interface | — | PCIe generation and x4/x8/x16 lane width are board-specific across current and legacy platforms. |
| VPX profiles | — | Payload and switch profiles; SOSA-aligned variants are available on selected 3U VPX products. |
| DATA PATHS & I/O | ||
| Mezzanine interface | — | VITA 57.1 FMC and VITA 57.4 FMC+ on selected carriers and VPX modules. |
| Data converters | — | Application-specific ADC, DAC, RF transceiver and direct-RF configurations. |
| Memory | — | DDR4, LPDDR4, QDR and boot flash resources vary by processing platform. |
| Clocking and trigger | — | Reference-clock, sample-clock, synchronization and external-trigger resources are product specific. |
| Networking | — | Ethernet and multi-gigabit serial links according to FPGA, transceiver and front-panel configuration. |
| DEPLOYMENT & SOFTWARE | ||
| Cooling | — | Air-cooled, rugged air-cooled and conduction-cooled options, platform dependent. |
| Software | — | Host drivers, DMA APIs, board-support packages and FPGA reference designs. |
| Standards | — | PCI Express, VITA 57.1/57.4 and VITA 46/65; SOSA alignment applies only to documented VPX products. |
Applications
RF and software-defined radio
Implement wideband acquisition, digital up/down conversion and spectrum processing on standard FPGA and converter platforms.
Radar and electronic warfare
Apply modular FPGA resources to beamforming, pulse processing, channelisation and signal-classification pipelines.
Semiconductor test
Combine protocol generation, synchronized stimulus, acquisition and hardware acceleration in configurable test architectures.
Machine vision
Route camera data through FPGA preprocessing toward GPU or storage pipelines with a defined DMA architecture.
Network acceleration
Implement packet processing, encryption, compression and deterministic data movement in programmable logic.
Research instrumentation
Reconfigure acquisition and generation pipelines while retaining a consistent board and software integration baseline.