PCIe Switches & Fabrics

Scale PCIe beyond one cable or one host by creating managed paths between computers, expansion systems, accelerators, storage and I/O endpoints.

Switch families

MXS524 · MXS924 · MXS824

Generations

PCIe Gen3 · Gen4 · Gen5

Port density

24 × x4

Aggregation

Up to x16

24-port switches Transparent I/O NTB fabrics Port aggregation Ethernet management Multi-switch topologies

Technical context: Dolphin MXS, MXP and MXC switch platforms support selected cabled, PXIe and CompactPCI Serial topologies. Port width, backplane generation, firmware mode and multi-host behaviour vary by model. MXS524 is currently published as a preliminary product; confirm orderability, firmware and supported functions before design-in.

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System Capabilities

PCIe switches provide fan-out, port aggregation and multi-host topology options when direct cable links no longer meet the system scope.

Additional ports and endpoints

Connect multiple hosts, expansion systems, accelerators or storage devices through a managed switching layer.

Transparent and NTB topologies

Support one-root-complex expansion or communication among independent hosts, depending on adapters and configuration.

Configurable lane allocation

Group x4 ports into wider links where the switch and connected hardware support the required mapping.

Central link visibility

Use supported management interfaces to inspect topology, negotiated links and selected PCIe errors.

Technical Features

Key platform elements and integration considerations are outlined below.

MXS524 Gen5 switch

A preliminary 1U PCIe 5.0 platform with 24 non-blocking x4 SFF-8614 ports. Up to four ports can be aggregated as an x16 link, providing up to 512 GT/s signalling per aggregated connection. Current published cable limits are up to 2 m copper and 100 m optical for this switch.

MXS924 Gen4 switch

A 1U PCIe 4.0 platform with 24 x4 SFF-8644 ports. Compatible ports can be grouped as x8 or x16 and used with transparent or NTB adapter families.

MXS824 Gen3 switch

A 1U PCIe 3.0 switch with 24 non-blocking x4 SFF-8644 ports, 32 GT/s signalling per x4 port and aggregation up to x16.

Transparent I/O fan-out

Connect one root complex to multiple remote endpoints or expansion systems while retaining native PCIe transactions.

NTB multi-host fabrics

Connect independent root complexes through NTB adapters for memory, messaging and software-defined communication.

Port aggregation and topology

Combine x4 ports as x8 or x16 and interconnect switches for larger fabrics. Oversubscription and hop count must be reviewed.

Management and firmware scope

Ethernet management supports firmware updates, configuration and status monitoring. Partitioning, failover and other advanced multi-host functions are firmware- and release-dependent and must be confirmed for the selected platform.

Specifications

Technical parameters and system-integration requirements are listed below. MXS524 values are preliminary and should be confirmed against the current product documentation before design-in.

PCIe Switches & Fabrics architecture and integration parameters
Parameter	Unit	Value / Description
SWITCH PLATFORMS
MXS524	—	1U PCIe 5.0 switch with 24 non-blocking x4 SFF-8614 ports; up to four ports may be aggregated as x16.
MXS924	—	1U PCIe 4.0 switch with 24 x4 SFF-8644 cable ports.
MXS824	—	1U PCIe 3.0 switch with 24 non-blocking x4 SFF-8644 ports.
Port aggregation	lanes	One x4, two-port x8 or four-port x16 connections, subject to the switch generation, firmware and cable mapping.
Adapters	—	Transparent and NTB adapter families matched to generation and cable interface.
FABRIC DESIGN
Traffic models	—	Host-to-device, host-to-host, peer-to-peer or mixed traffic.
Scale	—	Node count, switch count, hop count and simultaneous bandwidth.
Oversubscription	—	Aggregate endpoint traffic must fit the selected uplinks and switch paths.
Clocking	—	Clock isolation and cable-link clock handling depend on adapters and switch configuration.
OPERATIONS
Management	—	Ethernet-based configuration, monitoring and diagnostics on supported switch platforms.
Partitioning	—	Logical topology and advanced multi-host features depend on firmware and product configuration.
Recovery	—	Define link-loss, host restart, switch restart and topology reinitialisation behaviour.
Compatibility	—	All adapters, cables and switches must support the required generation, lane width and port mapping.

Applications

The architecture is most useful where native PCIe access, sustained data movement or tightly coupled multi-node communication materially affects the system.

Compute clusters

Create low-overhead PCIe communication fabrics for shared memory, sockets or direct-memory transfers between servers.

Accelerated systems

Fan out GPU, FPGA and acquisition resources to remote hosts or expansion domains using validated topology and ownership rules.

NVMe and storage paths

Build high-rate PCIe storage connections while accounting for peer routing, host resources and failure recovery.

Automated test

Aggregate controllers, PXIe chassis and external acquisition hardware across multiple racks.

Simulation platforms

Distribute state, sensor and actuator data among real-time, visualisation and recording nodes.

Data-intensive services

Scale tightly coupled caching, replication and analytics systems where local-fabric latency and bandwidth justify PCIe networking.