Map
NTB mappings establish translated address windows between independent hosts, after which eXpressWare exposes the configured memory, events and communication services.
Reference architecture · Independent hosts
Low-Latency PCIe Networking
Connect independent computers through non-transparent bridging and exchange data through SISCI shared-memory operations, SuperSockets or IPoPCIe according to the application and supported software release.
Root domains
Independent on every host
Bridge model
PCIe non-transparent bridge
Software paths
SISCI · SuperSockets · IPoPCIe
Topology
Direct or switched multi-node
Reference topology
NTB host networking
Host A
Independent root complex
Application and local memory
Host B
Independent root complex
Application and local memory
Host C
Independent root complex
Application and local memory
switch
NTB fabric
Translated address windows, interrupts and DMA
Control plane
PCIe data plane
Operating model
How the architecture works
The sequence describes system behaviour rather than a product feature list.
Transfer
Applications select SISCI shared-memory transfers using PIO or DMA, SuperSockets for socket-compatible applications, or IPoPCIe for standard IP networking where supported.
Coordinate
SISCI events or data interrupts, socket/IP semantics and application protocols provide notification, ownership and synchronization according to the selected software path.
System definition
Reference topology and architectural boundaries
Ownership, data movement, software responsibility and the limits of the pattern are defined separately.
System-level view
NTB host networking
Host A
Independent root complex
Application and local memory
Host B
Independent root complex
Application and local memory
Host C
Independent root complex
Application and local memory
switch
NTB fabric
Translated address windows, interrupts and DMA
Qualification required
Application-aware design
Ownership model
Independent hosts
Each computer keeps its own root complex and operating system.
Communication model
NTB windows and software APIs
Data crosses translated PCIe address spaces rather than one shared enumeration tree.
Software choices
Shared memory, sockets or IP
The software path determines application changes, latency, CPU overhead, operating-system support and interoperability limits.
Scale model
Direct or switched
Node count, port width, redundancy and switch partitioning define the fabric.
Engineering criteria
Design decisions that determine whether the architecture will work
These items must be resolved for the actual hosts, endpoints, operating systems, topology and workload.
Application interface
Choose SISCI for explicit shared memory, PIO, DMA and events; SuperSockets for socket-compatible applications; or IPoPCIe for standard TCP/IP and UDP networking where supported.
Transfer profile
Characterize message size, update frequency, burst behaviour, latency target, throughput and CPU budget.
Topology and failure model
Define direct links or switches, node count, redundant paths, fail-over ownership and restart behaviour.
Operating systems
Confirm the supported eXpressWare release, hardware family and operating-system combination. SISCI, SuperSockets and IPoPCIe have different platform and cross-system interoperability limits.
Observability
Plan fabric status, link errors, node health, transfer counters and application-level timeout diagnostics.
Implementation layers
Building blocks used to realize the architecture
The final system combines compatible hardware, software, application logic and validation—not one standalone product.
NTB adapters
Compatible host adapters or system modules operating in non-transparent mode.
PCIe fabric
Direct cable links or managed switches sized for node count and lane width.
eXpressWare
Drivers, fabric services and the selected application interface, with availability determined by hardware, operating system, licence and eXpressWare release.
Application protocol
Memory layout, messages, synchronization, events and recovery logic.
Time and availability
Optional clock/time distribution, health supervision and fail-over control.
Engineering evidence
Latency, jitter, throughput, load and recovery measurements under representative traffic.
Selection boundary
Where this architecture fits
Use the pattern when its ownership and data-movement model match the engineering requirement.
Use this architecture
Independent computers need lower communication overhead or higher throughput than a conventional software network path can provide.
Use another architecture
A single host only needs remote endpoints; transparent expansion is simpler in that case.
Typical deployments
Distributed acquisition, real-time processing, high-availability pairs, clustered storage and compute pipelines.
Project definition
Inputs required before system configuration
Architecture selection starts with the actual platform, traffic, software and recovery requirements.
Node inventory
Host count, PCIe slots, OS, CPU architecture and required redundancy.
Traffic model
Payload size, direction, frequency, burst profile and latency/jitter targets.
Software path
Shared-memory API, sockets, IP or a mixed migration strategy.
Recovery model
Node restart, link loss, fail-over, stale data and application resynchronization.
Define the topology before selecting the components.
Primionics can review the root-complex model, endpoint inventory, lane and bandwidth budget, software path, operating-system support and qualification requirements for the complete PCIe system.